An analog-to-digital converter (ADC) is an electronic device that receives an analog signal as an input and produces a digital representation of that signal as an output, i.e., it converts the analog signal to a digital signal. An ADC typically comprises an input buffer, a sample-and-hold or similar circuit, and an ADC element. The sample-and-hold circuit holds a sample of the analog signal for a time interval sufficient to allow the ADC element to perform the conversion process on the sample. The sample-and-hold circuit typically includes a clock input and associated switching circuitry, such as one or more transistors, to enable converting successive samples in a clocked manner.
In some ADC applications, it is desirable for two or more ADCs to operate in parallel with each other. That is, each of the ADCs in the system receives the same analog signal as the others and produces a digital representation of that signal. In theory, in such a system the digital value at the output of each ADC at any given instant in time will be the same as the digital value at the output of every other ADC. However, in actual circuit implementations clock skews can cause ADC outputs to differ from one another.
For example, as illustrated in FIG. 1, a first ADC 10 and a second ADC 12 receive as inputs the same analog signal (“ANALOG IN”) and clock signal (“CLOCK IN”). A first buffer 14 in first ADC 10 receives the analog signal. A second buffer 16 in second ADC 12 similarly receives the analog signal. When the clock signal transitions from a low state to a high state, it turns on a first transistor 18 in first ADC 10 and a second transistor 20 in ADC 12. Transistors 18 and 20 function as switches. When first transistor 18 is turned on, a sample-and-hold element 22 in ADC 10 receives and stores a sample of the analog signal at the output of first buffer 14. Likewise, when second transistor 20 is turned on, a sample-and-hold element 24 in ADC 12 receives and stores a sample of the analog signal at the output of second buffer 16. A first ADC element 26 in first ADC 10 performs an analog-to-digital conversion on the sample stored in sample-and-hold element 22 and outputs a first digital signal (“DIGITAL OUT1”). A second ADC element 28 in second ADC 12 similarly performs an analog-to-digital conversion on the sample stored in sample-and-hold element 24 and outputs a second digital signal (“DIGITAL OUT2”). However, the first and second digital signals may not be precisely the same value, due to clock skew or input signal skew. Skew can exist between the clock signal that reaches first transistor 18 in ADC 10 and the clock signal that reaches second transistor 18 in ADC 12. Similarly, skew can exist between the analog signal that reaches the input of first buffer 14 in ADC 10 and the analog signal that reaches the input of second buffer 16 in ADC 12. Such skews are mainly caused by differences in the lengths of the circuit traces that carry the signals, which correspondingly delay the respective signals by different amounts of time.
In some high-speed ADCs, multiple ADC elements are interleaved to increase the sampling rate of the conversion. Such an ADC may include additional inputs that allow DC offset, gain and clock timing of each ADC element to be adjusted so that the ADC elements operate uniformly.
It would be desirable to minimize the adverse effect of the skews so that both of the ADCs produce the same digital output value on a given clock cycle.